The present invention relates generally to field of electronic devices, and more particularly, to a universal synchronization clock and skew correction in a bus system.
In the field of electronics, a collection of wires or lines which connect several electronic devices is called a bus. Because a bus can effectively be shared by multiple devices, modern computer systems may incorporate one or more bus systems for the communication of data between devices. Such bus systems can be synchronous or a synchronous. A synchronous bus system utilizes a clock signal to time the transfer of data. In contrast, an a synchronous bus system does not utilize a clock signal for the transfer of data.
In general, synchronous bus systems allow data to be transferred more rapidly than asynchronous bus systems. Consequently, synchronous bus systems are widely used for high-speed devices (e.g., memory, hard disk drive, video controller, etc.), whereas asynchronous bus systems are preferred for low-speed devices (e.g., mouse, keyboard, etc.).
A significant problem with synchronous bus systems, however, is clock-data skew. Clock-data skew is a delay between a data signal and the clock signal used to time the transfer data carried by the data signal. Clock-data skew is caused mainly by a mismatch between a transmission line for the clock signal and the transmission lines of the data I/O buses. This mismatch may be attributable to differences in length, impedance, or other variables. In high-speed computer systems, the amount of clock-data skew may exceed the period of a clock cycle, in which case, the transfer of data becomes more complicated and difficult if a synchronous bus system is used.
A number of previously developed techniques have attempted to solve the problem of clock-data skew in a synchronous bus system. One previously developed technique limits the length of the clock line and the data bus so that clock-data skew cannot become very large. This is impractical, however, because modern computer systems require clock lines and data buses with relatively long lengths in order to support extensibility.
Another previously developed technique uses a plurality of clock sources within a bus system. Each clock source generates a respective clock signal which is output on its own clock line. Each clock line is connected to a separate device. In order to provide a reference clock with the same phase for all devices in the bus system, the clock lines must be matched so that the respective clock signals are synchronously received at the devices. A disadvantage of this previously developed technique for a bus system is its relative complexity. Because all clock lines must be perfectly matched, the system cannot be easily implemented in practice. Another disadvantage of the technique is that the operating frequency of the bus system depends on the propagation delay of the data bus. As the length of the data bus is extended, the system operation frequency must be slowed.
With yet another previously developed technique for a synchronous bus system, the clock line, all data buses, and all control buses must be perfectly matched. With this arrangement, all data and control signals travel on the respective buses in a constant phase relationship with respect to the clock signal. Accordingly, clock-data skew is reduced. A disadvantage of this previously developed technique is the requirement that all signals be perfectly matched. More specifically, in a printed circuit board (PCB) design, it is very difficult to match all signals due to various uncontrollable factors, such as variation in the length and width of the bus, mismatch of material characteristics, and corner effects of the bus.
The disadvantages and problems associated with previously developed techniques for a bus system to the transfer data between devices have been substantially reduced or eliminated using the present invention.
More particularly, the present invention relates to a bus system wherein skew correction circuitry and synchronization clock circuitry are provided. The skew correction circuitry minimizes the clock-data skew to avoid errors, and the synchronization clock circuitry generates a universal synchronization clock signalxe2x80x94comprising a universal synchronization clock transmission (USTXCLK) signal and a universal synchronization receive clock (USRXCLK) signalxe2x80x94for synchronizing the transmission of data in the bus system.
The synchronization clock circuitry, in one embodiment, is coupled to a clock line having two segments: a forward direction clock (FDCLK) segment and a reverse direction clock (RDCLK) segment. The FDCLK segment carries an FDCLK signal, and the RDCLK segment carries an RDCLK signal. The synchronization clock circuitry uses the FDCLK and RDCLK signals to derive the universal synchronization clock signal, which is synchronous throughout the system.
The skew correction circuitry, in one embodiment, can be provided for each data input/output (I/O) pin of a slave device. The skew correction circuitry may generate a transmission (TX) clock signal to correct for skew between the universal synchronization clock signal and an outgoing data signal, and a reception (RX) clock signal to correct for skew between the universal synchronization clock signal and an incoming data signal.
According to an embodiment of the present invention, a synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals.
According to another embodiment of the present invention, a synchronization clock circuitry includes a multi-phase clock generator circuit for generating a plurality of clock signals, each of which has a different phase. The multi-phase clock generator circuit receives a forward direction clock signal. A controller identifies a difference in phase between the forward direction clock signal and a reverse direction clock signal, and generates a control signal. A first phase selector circuit, coupled to the multi-phase clock generator circuit and the controller, selects one of the plurality of clock signals as a universal synchronization clock signal in response to the control signal.
According to yet another embodiment of the present invention, skew correction circuitry includes a reception data synchronizer circuit and a transmission data synchronizer circuit. The reception data synchronizer circuit corrects for skew between an incoming data signal and a universal synchronization clock signal. The transmission data synchronizer circuit corrects for skew between an outgoing data signal and the universal synchronization clock signal.
The present invention affords numerous technical advantages. One technical advantage includes providing a synchronous bus system in which the clock line does not have to be matched with the data bus in order to operate properly. This allows a relatively long clock line to be provided in the synchronous bus system, thus allowing greater extensibility of the system. Another technical advantage of the present invention includes deriving a universal synchronization clock signal which can be used as a reference clock by all devices in the synchronous bus system. Yet another technical advantage of the present invention includes compensating or correcting for the clock-data skew caused by any mismatch between the clock line and data I/O buses to avoid errors in the synchronous bus system. Still another advantage of the present invention includes minimizing or eliminating the skew between multiple data I/O lines in a synchronous bus system with a long data bus. Still yet another technical advantage of the present invention includes synchronizing all data I/O transactions to the universal synchronization clock signal in the high-speed, synchronous bus system. Other important technical advantages of the present invention are readily apparent to one skilled in the art from the following figures, descriptions, and claims.